Fully digital receiver equalizers, using finite impulse response (FIR) filters, require high-resolution sampling ADCs that run at GHz speeds, which is a quite challenging task in present CMOS technologies, and conceptually can burn a lot of power. The basic elements of a FIR filter are delay elements, adders, and multipliers to implement the following FIR equation:Veq(n. t s)=Vi(n.t.s)+αVi(n−1).t s)+βVi(n−2).t s)+ . . .
The disadvantage with most analog continuous-time equalizers is that they need very wide-bandwidth delay elements that run at the same speed as the input data, and therefore burn considerable power. Input equalizers, reported to date in CMOS technology (toward main stream process and low power), operate at data rates around 1-2 Gbps (1). Therefore, in low-power applications where multi-gigabit/s (2.5→10 Gbps) equalizers are required, speed limitations of the CMOS process make it impractical to implement FIR equalizers in the traditional digital or analog methods.
Accordingly, what is needed is a system and method for providing very low-power equalization for circuits operating on the Gbps range. The equalization should be easy to implement, cost effective and compatible with existing technology. The present invention addresses such a need.